SG2000 Hints

Notes and slides for working with the Sophgo SG2000 (Milk-V Duo S) in CS 4250 — Computer Architecture.

Hints

Setup — flash the image, enable passwordless SSH and sudo.
Running Arduino sketches on the second core — build a sketch and load it onto the little C906 core via remoteproc.
Physical memory access from a sketch — why the little core is M-mode/physical, and a test plan for raw DRAM and peripheral access.
Controlling GPIOs with assembly — drive the J3 pin 7 LED (XGPIOB18) from inline RISC-V asm, with and without the Arduino core.
How a GPIO pin is controlled: Linux, Arduino, mmap, and pure asm — one pin, four layers of abstraction, as a type-along lecture runbook.
The 8051 “MCU” — the third core: what the always-on 8051 can do, why our images ship no firmware for it, and what custom firmware would add.
The TPU — the 0.5 TOPS INT8 engine: what it can and cannot compute, the five-layer vendor stack, why “TPU development” has no standard, and the zero-sized ION carveout that stops the whole thing from running.

Why an OS? From Blink to FreeRTOS on the SG2000 Little Core — motivating OS services on a real-time secondary core: six coordination problems and the services that answer them.
Why an OS? — Reference Notes — a condensed version.

Porting the SG2000 Debian Image to the Oz64 — device tree changes and getting the AIC8800DC WiFi working.
Oz64 Port — Reference Notes — a condensed version.

I²C: Two Wires, Many Chips — from a serial protocol to driving an SSD1306 OLED on the SG2000/Oz64.
I²C — Reference Notes — a condensed version.

Beyond the CPU: Clocks, Power, DMA, and the Engines — the machine around the CPU: the clock tree, the always-on power island, the DMA engine, carveouts/ION, and a quick tour of the accelerators.
Beyond the CPU — Reference Notes — a condensed version.

Caches and the Memory Hierarchy — the stock cache story from transistors to associativity, then four real cores compared: both C906s, the Cortex-A53, and a Ryzen 7 9850X3D.
Caches and the Memory Hierarchy — Reference Notes — a condensed version.

Pipelining: One Instruction Per Clock — the five-stage Beta, the three strategies for data and control hazards, and what the C906’s in-order pipeline actually implements.

GPUs and the Throughput Machine — latency versus throughput, SIMT, the inverted memory hierarchy, and why a GPU is a card: PCI, PCIe, BARs, and what the sg2000 would have to change.
GPUs — Reference Notes — a condensed version.

The Neural Processor — the sg2000’s 0.5 TOPS INT8 engine: an operation list instead of an instruction set, a device that was present and unusable, one matmul measured on both machines, and a text-to-speech pipeline split across two processors.
The Neural Processor — Reference Notes — a condensed version.